01 / GENERATE THE FIELD
A compact origin.
Generate structural values from a defined seed and rule set. Matrix Controllers express the resulting field through a compact, regular interface.
GENERATIVE TOPOLOGICAL COMPUTINGAddressing.
Routing. Recovery.Unified by
generative algebra.
A generative, nonlinear computing fabric that integrates addressing, scale-aware routing, multi-layer verification, and structural recovery into a unified multi-radix algebraic framework.
Different functions. Different resolutions.
One mathematical grammar.
Mathematical foundationsProgrammatic validationFPGA development
THE NONLINEAR DATAFIELDSEED → SHARED FIELD
DYADIC1 × 1
TRIADIC1 × 1
ONE GENERATIVE SEED
DRAG TO ROTATE · RELATED SCALE VIEWS
ONE FABRIC. EXPLORE ITS FUNCTIONS.Choose a function to jump into the field.
WATCH THE STRUCTURE FORM
Two scale progressions. One shared field.
The dyadic and triadic views emerge together, keeping earlier resolutions visible as the native field takes shape.
DYADIC 1 → 2 → 4 → 8 → 24
TRIADIC 1 → 3 → 6 → 12 → 24
SELECTED NATIVE SEAT
Select a visible node in the field.
FIELD-WIDE ROUTING
All circuits in each pattern activate together.
Follow the paths across the whole field.
CONTINUOUS SCALE TOUR
Each resolution takes its turn in green.
Every field stays present.
IDENTITY & CIRCUIT AGREEMENT
Operator fieldAnchor fieldStructural node
Operator reportAnchor responseNode agreement
TOROIDAL ∑
POLOIDAL ∑
Awaiting reportsIllustrative semi-magic checksum · example values
ILLUSTRATED RECOVERY
FROM A SEED TO A SHARED STRUCTURE
Different views of one fabric.
A compact generative description produces structural relationships. Supported scale views organize those relationships at different resolutions, while a common control grammar connects addressing, geometric operations, verification, and eligible structural recovery.
What this graphic shows
The growth and scale-tour views are separated visually to make their resolutions readable. Their display spacing is illustrative; the verification role fields use the declared hierarchy. Live address and circuit controls use public coordinate relationships; private controller values, generating equations, and kernel coefficients are not included.
Verification and recovery
Verification illustrates operator and anchor reports converging on a structural node, followed by its toroidal and poloidal ring checks. The semi-magic checksum uses a separate synthetic example, not Torus³ controller values. The verification fields follow the declared structural, operator, and embedded-anchor role proportions. Yellow identifies the operator field; red identifies the embedded anchor field. The reporting paths illustrate shared context. Recovery remains a visual walkthrough of evidence-dependent outcomes. Neither walkthrough executes private controller verification or recovery logic.
SEPARATE LAYERS. ONE MATHEMATICAL STRUCTURE.Seed → Scale → Shared functions
01 / WHAT IS BEING UNIFIED
Mapping
infrastructure to
Logic.
Multiple functions. One Control Grammar.
The relationships that generate the Torus³ datafield also organize its addresses, define routes, connect scales, check consistency, and support structural recovery.
Matrix Controllers and Universal Scale Kernels express these functions through one shared mathematical grammar. Each operation draws on connected relationships in the same fabric.
COMPUTATIONAL FUNCTIONSSELECT A FUNCTION
SHARED GENERATIVE FRAMEWORK
One mathematical structure
Matrix Controllers Universal Scale Kernels
SHARED GENERATING RULESCONNECTED STRUCTURAL CHECKS
LOCATION + CONTEXT
Give every location its context.
A location stays identifiable as the view changes. The fabric carries its controller, position, and view context together, keeping the address connected to the same underlying field.
Complete address context distinguishes field and plane identity as coordinates are reinterpreted. Supported transformations preserve the information needed to resolve and return to the original address.
Follow the field’s relationships.
Navigate repeatable paths defined by the structure. Supported reversible steps retain the context needed to trace a route back to where it began.
Compose coordinate movement, orientation changes, plane changes, and complete scale charts. Supported bijective steps undo in reverse order while preserving the required structural context.
Connect the region to the node.
Move between broad regions and local detail while keeping their relationship intact. Coarse and fine views belong to the same generated field.
Partition and aggregate the Matrix Controller into coarser views. Universal Scale Kernels connect retained lineage and target context to finer structural values; complete address charts retain the local position.
Repair through surviving relationships.
Use surviving structural relationships to reconstruct missing state. The recovery policy checks whether the available evidence supports a repair before applying it.
Eligible circuit relationships and retained parent context constrain candidate structural values. The recovery policy distinguishes supported repairs, insufficient evidence, and conflicting observations.
Check consistency from connected views.
Compare several related observations of the same structure. Their agreement supports verification, while differences make inconsistencies visible.
Symmetry, recurrence, whole-integer conservation, and supported row-and-column checks provide related structural witnesses. Their observations are evaluated within the declared controller and scale context.
One field, interpreted through connected operations and observations.
02 / OPERATE THROUGH VIEWS
A connected control grammar.
Select a location, follow a route, or change resolution using related controls. Different views operate on the same underlying structure while retaining the context each operation needs.
03 / CHECK THROUGH RELATIONSHIPS
Verification is connected.
Compare symmetry, recurring patterns, and conserved totals to check structural consistency. When sufficient surviving evidence agrees, those relationships can also support recovery.
0:00 / 1:12
02 / TORUS³ / PLATFORM CAPABILITIESAn Integrated
An Integrated
Computational Fabric.
Demonstrated together on an FPGA: generative structure, multiscale controls, views of unchanged stored data, and evidence-dependent structural recovery. Explore what each capability does and the tests behind it.
Technical review · accepted FPGA campaign
Accepted physical benchmark
Digilent Arty A7-100T · 100 MHz
Build 47B7141D · verified 25 September 2026
Engineering status current through 2 October 2026.
Integrated result
Generative structure, multiscale kernels, immutable-payload views, and SymmetriTek structural recovery passed in the same deployed bitstream.
Resource scope
10,845 logic LUTs · 7,968 flip-flops · 0 DSPs · 0 structural lookup-table BRAM.
Payload: 81 KiB logical store in 32 RAMB36 blocks. Structural recovery: one additional RAMB18.
Development boundary
The newer routing benchmark has passed simulation and synthesis but currently fails the 100 MHz implementation timing requirement. On-board routing-depth results remain pending.
How to read these results: Counts cover related and sometimes overlapping workloads. Do not add them into one cumulative total. The measured identity-view timing is an internal baseline; competitive speed and measured energy advantages remain unestablished.
Structural generation & mapping
Generate the structure. Give every location its context.
Seed-Generated Topology
Generate the structure as needed.
Creates the fabric’s structural values from a compact starting description. The FPGA calculates relationships as they are needed, supporting an expanded field without a stored structural lookup table.
FPGA DemonstratedReference Matched
Technical evidence for Seed-Generated Topology
186,624structural outputs across nine family fields
Expanded generation
The accepted 144×144 kernel campaign includes 186,624 structural outputs across nine family fields.
Hardware evidence
These outputs belong to the passing kernel campaign in build 47B7141D on the Digilent Arty A7-100T at 100 MHz, verified 25 September 2026.
Scope: Structural outputs describe the generated layout. Application payload remains separately stored. These outputs overlap the kernel workload and are not an additional campaign total.
Nonlinear Address Space
More ways to view the same data.
Exposes alternate arrangements of the same stored data. Each complete tested view preserves every underlying reference, allowing the system to change how data is addressed while keeping the original data in place.
FPGA DemonstratedReal Payload Tested
Technical evidence for Nonlinear Address Space
24 complete planes20,736 positions scanned in every plane
Permutation-plane coverage
Each of the 24 permutation planes received a complete 20,736-position scan over real payload. Every scan retained each underlying reference exactly once.
Result
The tested plane views preserved the complete reference set without missing or duplicated references. Payload-view correctness and unchanged storage were checked in the integrated campaign.
Scope: These are logical views of existing stored data. They do not create additional physical storage capacity.
Controller-Braid Expansion
A larger fabric, still connected.
Builds a larger field by interleaving complete controller networks. The FPGA generates and addresses this expanded structure through shared logic, preserving the relationships that connect its controllers.
FPGA DemonstratedInterleaved Fabric Tested
Technical evidence for Controller-Braid Expansion
144×14436 complete interleaved 24×24 controller fibers
Construction tested
The expanded construction contains 36 complete interleaved 24×24 controller fibers, spanning 20,736 positions per family field.
On-board coverage
Nine family fields produced 186,624 structural outputs within the passing kernel campaign. This is hardware evidence for the tested 144×144 construction.
Scope: These are interleaved controller fibers, not separate per-node compute engines. The output count is shared with the generation and kernel evidence; larger constructions require their own qualification.
Operations, scaling & self-healing
Change the view, preserve context, and recover supported structural state.
Geometric Processing
Change orientation and context.
Combines supported position, orientation, and scale changes within one set of controls. Tested combinations preserve the expected relationship to the underlying data and retain the context needed for supported returns.
FPGA DemonstratedComposed Controls Tested
Technical evidence for Geometric Processing
Offsets + symmetriescomposed controls across nine family contexts
Control coverage
The campaign covered all nine family contexts, offset labels 0–23, eight local symmetry operations, and eight whole-field symmetry operations.
Composed operations
Coverage included 64 ordered scale-chart pairs across 24 planes. Supported combinations were checked against their expected relationships and return context.
Scope: These are tested address and control transformations. On-board routing-depth measurements are a separate benchmark and remain pending.
Error Correction & Recovery
Repair when the evidence supports it.
Reconstructs supported damaged structural state from surviving relationships. When the available evidence is insufficient or contradictory, the system refuses an unjustified repair instead of treating it as a successful recovery.
FPGA DemonstratedRefusal Behavior Tested
Technical evidence for Error Correction & Recovery
774 cases104,352 records in the SymmetriTek campaign
Recovery outcomes
The campaign recorded 684 survivor-based recoveries, nine regenerations, and nine healthy cases.
Evidence-dependent handling
It also recorded 45 insufficient-evidence outcomes and 27 conflict refusals. These distinct outcomes are included in the 774-case campaign.
Scope: This evidence covers the tested structural state and supported fault conditions. Trusted regeneration is distinct from survivor-based recovery; arbitrary payload-data recovery is not established by these tests.
Multiresolution Controller
Move between broad and fine views.
Interprets locations at different supported scales while keeping their context connected. The FPGA can use a broader view and return to the correct fine-scale context within the tested operations.
FPGA DemonstratedUniversal Scale Kernels Tested
Technical evidence for Multiresolution Controller
10,782 cases467,280 exact output records
Multiscale and kernel results
The accepted campaign covered multiscale operations and Universal Scale Kernels with 10,782 cases and 467,280 exact output records.
Return checks
Coverage included 47,880 scale-chart round trips and 12,672 aligned returns, checking the supported transition back to the correct fine-scale context.
Scope: These counts describe related and overlapping work within the same campaign. A scale view retains required address context; a coarse aggregate alone does not preserve every fine value.
Implementation, concurrency & auditing
Show what ran in hardware and what remains in development.
Compact Generative Logic
Generate layout. Store the payload.
Uses shared logic to generate structural relationships, with no block RAM devoted to structural lookup tables. The integrated design still uses memory to hold real application data and the structural state used for recovery.
FPGA DemonstratedNo Structural Lookup BRAM
Technical evidence for Compact Generative Logic
0 structural lookup BRAMresource scope: accepted integrated build 47B7141D
Integrated logic resources
The accepted design used 10,845 logic LUTs, 7,968 flip-flops, and zero DSPs, with zero structural lookup-table BRAM.
Payload and recovery memory
An 81 KiB logical application-payload store was implemented with 32 RAMB36 blocks. Structural recovery used one additional RAMB18 block.
Scope: The logical payload capacity and allocated block-RAM primitives are different measurements. Zero structural lookup-table BRAM does not mean the whole system uses zero memory. These are integrated-build resources, not the earlier standalone-core counts.
Regional Parallel Processing
A direction for future execution.
The shared structural context provides a basis for coordinating work across regions. Independent concurrent execution, its scheduling behavior, and its throughput remain a separate hardware development and qualification task.
In DevelopmentArchitectural Foundation
Technical evidence for Regional Parallel Processing
Concurrency pendingindependent regional execution still needs qualification
What the integration establishes
Payload, kernel, and recovery services passed in the same deployed bitstream. This establishes integrated service operation in the tested campaign.
What remains to be tested
Independent regional lanes, concurrent schedules, synchronization behavior, and parallel throughput require dedicated hardware evidence.
Scope: Passing service transitions does not establish simultaneous regional execution or a parallel performance advantage.
Deterministic Auditability
Results you can trace and check.
Makes tested behavior checkable against expected results. The campaign records distinguish successful views and recoveries from rejected requests, insufficient evidence, and conflicting observations.
FPGA Campaign EvidenceExpected Outcomes Checked
Technical evidence for Deterministic Auditability
36 negative testsexpected payload error outcomes behaved correctly
Accepted physical campaign
The latest accepted physical benchmark used build 47B7141D on the Digilent Arty A7-100T at 100 MHz, verified 25 September 2026. This page reflects the engineering status through 2 October 2026.
Checks and refusals
The campaign checked exact payload-view results and readback, recovery outcomes, and 36 expected payload negative tests. Tested invalid or stale requests were rejected as expected.
Scope: Reference agreement and expected refusals cover the recorded test conditions. Counts across these cards overlap and must not be added into a cumulative test total.
Payload, integration & routing
Keep stored data intact. Connect the services. Qualify the next step.
Immutable Payload Views
New arrangements. Unchanged data.
Retrieves data through alternate views while preserving the original stored words. The tested transformations use the existing payload store, without requiring a separate field-sized copy for each transformed arrangement.
FPGA DemonstratedZero Writes While Sealed
Technical evidence for Immutable Payload Views
973,968 view resultsthree real payload fixtures; zero mismatches
Payload correctness
The campaign checked 973,968 view-result records across three payload fixtures, with zero mismatches.
Before-and-after storage
A further 124,416 before/after readback words confirmed the tested storage contents. The campaign recorded zero writes while the payload was sealed.
Scope: No field-sized transformed payload copy is required for these tested views. The original payload still occupies memory, and the sealed-write result applies to the tested sealed intervals.
Integrated FPGA Services
The functions work together.
Runs payload views, scale-kernel operations, and structural recovery in the same deployed design. Tested transitions between services preserve the payload, with invalid or stale requests handled as expected.
Integrated FPGA PassPayload Retained
Technical evidence for Integrated FPGA Services
One deployed bitstreampayload, kernel, and recovery services passed together
Integration result
The accepted build passed payload, kernel, and recovery services together, retained payload through service transitions, and passed 36 expected payload negative tests.
Measured internal baseline
One complete 20,736-word identity-view batch took 3,109,104 FPGA cycles: 31.09104 ms at 100 MHz. This measurement excludes UART transfer and PC processing.
Scope: The timing is an internal identity-view batch baseline, not a per-word latency or competitive speed claim. Measured energy advantages and competitive performance advantages remain unestablished.
Intrinsic Multiscale Routing
The next hardware milestone.
A dedicated routing benchmark is in development. It has passed simulation and synthesis; meeting the target timing requirement is the next step before on-board routing-depth results can be established.
In DevelopmentSimulation + Synthesis Passed
Technical evidence for Intrinsic Multiscale Routing
On-board results pendingimplementation does not yet meet 100 MHz timing
Stages completed
The new intrinsic multiscale routing benchmark passed local simulation, Windows/Vivado simulation, and synthesis.
Current implementation status
Implementation currently fails the 100 MHz timing requirement. No accepted on-board routing-depth results are available from this benchmark.
Scope: The accepted integrated build’s results do not qualify this newer routing implementation. Low-hop hardware results, competitive speed advantages, and measured energy advantages remain pending.
Working FPGA integration. Defined test scope.
Evidence updated 2 October 2026 · accepted physical benchmark verified 25 September.
Open Technical evidence for build details, measured results, resource use, and test limits. Routing and regional concurrency remain in development.
03 / THE CORE ARCHITECTURE
One structure. Multiple views.
One relationship engine.
Embedded Matrix Controller
A seed-generated integer controller for configuring, addressing, and operating the fabric. It derives structural values on demand and supplies the location context used by the platform’s transformations.
Nonlinear Datafield
The Datafield expresses the Matrix Controller as a toroidal manifold through the system’s geometric ratios. It reveals the same structural locations through overlapping scale views, with one underlying layout.
The logic that activates relationships within the fabric. It combines arithmetic, symmetry, aggregation, phase, and scale operations into a closed, repeatable grammar for routing, verification, and structural recovery.
LINEAR VIEW
Matrix Controller
SELECTED ADDRESS · 5, 8CLICK TO SELECT
NONLINEAR VIEW
Nested Datafield
SAME LOCATION · 5, 8DRAG TO ROTATE
SAME LOCATIONS · SHARED CIRCUITS
CONNECTED PATHS
Follow the fabric’s circuits.
Activate a circuit pattern across the controller and see the same paths in the field. The geometry makes their connections visible.
HEXAGONAL CIRCUITS
INTERLEAVED POSITIONS
16 positions → 1 coarse node
SHARED ROW & COLUMN WRAP
THE RELATIONSHIPS, PUT TO WORKAddress. Route.
Address. Route.
Recover. Verify.
Multiple connected capabilities funtioning through the the same structural control grammar.
0 BRAMUsed by the tested
fabric logic.
fabric logic.
Generative address space
Generate a self organizing & self hierarchical address & context from compact rules.
Scale-aware routing
Connect coarse regions with exact fine locations through Universal Scale Kernels.
Consensus verification
Each node participates as a seed in a embedded controller matrix which utilizes overlapping circuits to form a consensus.
Self-healing recovery
Reconstruct supported structural states when surviving evidence agrees. Restored context can support further eligible repairs.
How to read the views
Phases select; scales group. A phase selects distributed positions at a chosen spacing. A scale view groups a contiguous region under a coarse node while retaining the fine location context for expansion.
Permutations reindex. The selected field location stays fixed while its visible row and column change with the wrapped origin. Both axes wrap together; reversing the wrap restores the prior indexing.
Nested views remain present. Faint fields show the supported dyadic and triadic progressions. Their display spacing separates the views for readability. This public illustration shows coordinate relationships without controller values or numerical aggregation results.
04 / DATA–FABRIC COUPLING
One payload.
Many ways to read it.
Use the mathematical structure as a reading filter: change the plane, work by region, or follow matching positions across the field. The requested view changes. The original stored words stay in place.
01 / SINGLE SOURCE
Stored payload
16 × 16 sample wordsSame words. Same locations.
Mathematical read filter
Compose an address view over the source.
Shift read origin
02 / RESOLVED READOUT
Composed view
256 referencesComplete view
Requested view position—
Resolves to the selected source.
Retained scale context—
Region + position within it.
Original stored reference—
Fixed physical sample location.
Unchanged stored word—
Read directly from the source.
Payload sealChecking…
Payload writes after sealing—
References in this view—
Duplicate references—
Three simultaneous views. One payload store.
Choose a view to inspect it above.
Public illustration with synthetic payload and generic address maps. Region and phase selections read subsets; they do not average or discard the stored data. On-board evidence is listed below.
Transform the relationship.
Preserve the data.
The FPGA campaign went beyond mirrored images: it tested complete permutation-plane scans, scale-aware controls, composed views, and unchanged real payloads within one deployed design. The useful distinction is that a new view can resolve references into the existing store without a field-sized transformed payload copy.
Technical evidence & how this illustration works
Recorded FPGA payload evidence
- 24 permutation planes: a complete 20,736-position scan per plane, retaining every reference exactly once.
- 973,968 view-result records: three payload fixtures, zero mismatches.
- 124,416 before/after readback words: zero mismatches and zero writes while sealed.
- Integrated services: payload, kernel, and recovery passed in the same bitstream; 36 expected payload negative tests behaved correctly.
Scale and composed-control evidence
- 10,782 cases / 467,280 exact output records in the multiscale and Universal Scale Kernel campaign.
- 47,880 scale-chart round trips and 12,672 aligned returns.
- Coverage included nine family contexts, supported offsets and local/whole-field symmetries, and 64 ordered scale-chart pairs across 24 planes.
- These are related and sometimes overlapping workloads. The counts must not be combined into one cumulative test total.
What the live controls actually do
The source is a frozen 16×16 fixture of synthetic 32-bit words. A view resolves each requested position to a source reference, then reads that existing word. Frame shifts wrap; region grouping keeps the region and within-region position; phase selection reads the same within-region position across regions. All-reference arrangements are reversible permutations. A selected region or phase is a subset of the intact source, not a compressed encoding from which omitted data can be recovered.
Public-model boundary
This model uses generic coordinate maps to explain immutable binding and complete scale context. It does not reproduce the private controller recurrence, FPGA plane implementation, Universal Scale Kernel circuitry, or hardware timing. Display buffers are used to draw the views; no second transformed payload store is built. The fingerprint is a demonstration check, not the system’s structural verification mechanism. Current source fingerprint: —.
Hardware provenance: Digilent Arty A7-100T at 100 MHz, accepted build 47B7141D, verified 25 September 2026; engineering status through 2 October 2026. The integrated design used an 81 KiB logical payload store in 32 RAMB36 blocks, plus one RAMB18 for structural recovery; structural lookup-table BRAM was zero. This is not a zero-memory system. This illustration supplies no hardware speed or energy measurement.