Node PerspectiveMultiplexed Scale-Aware Routing
Torus³ HyperRoute
Benchmark evidence for a software-defined topological routing fabric powered by the RouTOR³ Protocol. This public package presents the nonlinear address space capacity scaling law, route-depth evidence, load-diffusion evidence, and validation checks without exposing protected Torus³ sequences or private routing grammar.
Public Capacity Law
HyperRoute does not publicly claim that it stores billions of explicit address entries. The benchmark validates the opposite: the address space is generated structurally through a compact controller model rather than enumerated as a flat directory.
2D controller surface: N² Scalar carrier surface: 6N² Nonlinear address space capacity: 6N³ Minimal flat directory model: 6N³ × 16 bytes
768×768 Expansion Result
| Metric | Result | What it means |
|---|---|---|
| Controller side | 768×768 | Expanded public controller-domain model. |
| Base controller tiles | 1,024 | Number of 24×24 controller tiles in the 768×768 progression. |
| 2D controller surface, N² | 589,824 seats | Linear matrix-controller surface area. |
| Scalar carrier surface, 6N² | 3,538,944 seats | Public scalar-family carrier model. |
| Nonlinear address space capacity, 6N³ | 2,717,908,992 address states | Tensor-lifted nonlinear address capacity generated by the public law. |
| Minimal flat directory model | 43.49 GB | Explicit enumeration at 16 bytes per address state. |
| Capacity vs scalar carrier surface | 768× | Nonlinear capacity divided by scalar carrier seats. |
| Capacity vs controller surface | 4,608× | Nonlinear capacity divided by raw 2D controller seats. |
Generated Controller vs Flat Directory
| Representation | Approx. size | Public comparison vs flat directory |
|---|---|---|
| Generated 2D controller surface, 1 byte/seat | 0.59 MB | 99.9986% smaller |
| Generated 2D controller surface, 4 bytes/seat | 2.36 MB | 99.9946% smaller |
| Scalar carrier surface, 4 bytes/seat | 14.16 MB | 99.9674% smaller |
| Full-family carrier surface, 4 bytes/seat | 21.23 MB | 99.9512% smaller |
| Minimal flat directory, 16 bytes/address | 43.49 GB | Baseline |
Public wording: at 768×768, HyperRoute’s generated 2D controller surface is approximately 99.9986% smaller than a minimal flat directory model for the same nonlinear address space capacity. A conservative 9-family, 4-byte-per-seat carrier representation remains approximately 99.95% smaller.
Additional Prototype Benchmark Evidence
| Benchmark | Current result | Interpretation |
|---|---|---|
| Route depth | 2.82 average steps; max 3; ~1.48 µs average Python controller decision time | Controller-level route planning remains shallow without requiring a massive flat route table. |
| Load diffusion | 50,000 routed samples; 2.52 average path steps; P95 node load 2; max node load 10 | Randomized route pressure spreads broadly across logical route states in the prototype stress test. |
| Collision separation | 200,000 contexts; 0 full nonlinear address collisions; max visible-coordinate reuse 10 | Visible-coordinate reuse is separated from full nonlinear address-context collision. |
| Payload verification proxy | 200,000 payloads; 40,000 corrupted; 100% detected; 100% final exact recovery | Manifest-backed prototype supports exact corruption detection and recovery when payload binding is present. |
| Public validation | PASS — 34 checks passed, 0 failed | Open validator checks public arithmetic and reporting consistency without exposing protected mechanics. |
Public Validation Model
The benchmark package is designed for black-box or gray-box review. It exposes results and validation checks, not proprietary Torus³ generation mechanics.
Protected HyperRoute Engine
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Redacted Raw Benchmark JSON
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Open Validator Script
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Validation Report
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Website Benchmark Summary
Technical Boundaries
Current HyperRoute benchmarks are internal prototype / controller-level results. They validate public formula capacity, routing behavior, address-space modeling, collision separation, payload verification, and public telemetry consistency. They do not yet claim production hardware latency, ASIC/FPGA timing, independent cryptographic certification, or third-party reproduced performance. Deeper technical review can be performed through a closed-engine benchmark run under NDA.